Structure for a semiconductor resistive element, particularly for high voltage applications and respective manufacturing process

ABSTRACT

A structure for a semiconductor resistive element, applicable in particular to power components, having a high concentration substrate of the n type, a first epitaxial layer of the n type, a region of the p type arranged on said first epitaxial layer so to form the resistive element proper, a second epitaxial layer of n type grown on said first epitaxial layer to make the region of the p type a buried region, and an additional layer of the n type with a higher concentration with respect to the second epitaxial level, positioned on the embedded region. Low resistivity regions of the p type adapted to make low resistivity deep contacts for the resistor are provided. The buried region can be made either with a development that is substantially uniform in its main direction of extension or so to present, at on part of its length, a structure of adjacent subregions in marginal continuity. In this way, either a resistive element presenting a substantially linear performance in all ranges of applied voltage or a resistive element presenting a marked increase of the resistance value as the applied voltage increases can be made. This all with the additional possibility of selectively varying the resistance value demonstrated before the increase.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention relates to semiconductor resistive elements and wasdeveloped with particular attention to the possible use in high voltageapplications.

[0003] 2. Description of the Related Art

[0004] In general, in monolith semiconductor power apparatus, such asthose made with VIPower technology developed by the Applicant, the needexists for having the substrate voltage partitioned within the controlregion of the apparatus.

[0005] This function can be obtained, for example, by means of aresistor connected between the substrate and the control region in whichthe substrate voltage is to be detected.

[0006] In power applications, the substrate can reach rather highvoltage values (up to 2000 V) and the resistor connected therewith mustbe capable of withstanding the same voltage.

[0007] Particularly, when referring to resistive structures capable ofdetecting the voltage on an electrode (collector or drain) of a powercomponent in monolith integrated semiconductor devices, the use ofresistors destined to have high voltage applied to their terminalsentails the need to make these resistors with a particularly highelectrical resistance, for example higher than 100 KOhm.

[0008] Such high resistance values imply the use of considerably highresistance and/or long layers. Consequently, also when employing layerswith the highest resistivity in technology, the integration of highvoltage resistors implemented according to the prior art requires alarge area of silicon.

[0009] For example, a serpentine resistive structure integrated on asemiconductor substrate is described in previous European ApplicationEP-A-0996158.

[0010] A disadvantage of this type of structure is that the distances tobe kept between one branch of the serpentine and another must be greaterthan the space-charge region which extends in the substrate. Since thesubstrate presents a low doping level, the dimension of this region isin the order of tens of microns when a high voltage difference isapplied. An additional loss in terms of occupied area is produced inmaking annular regions or field plates of low concentration dopedsilicon surrounding the resistor to prevent premature breakdowns.Another problem related to this kind of resistor is the interaction withthe on-board apparatus structures where they are inserted.

[0011] Another type of high voltage resistor of a known type employs ahigh resistivity semiconductor layer with conductivity opposite to thatof the substrate surrounded by a layer of insulating material, forexample silicon dioxide. This solution solves the problem of thespace-charge region which would tend to short-circuit the facingbranches of the resistor. This is because the depth of the insulatingmaterial regions is sufficient to prevent this event. However, thissolution requires that the resistor be located near the high voltageregion of the apparatus and only slightly reduces the occupied area.Furthermore, the possibility of interaction with the structures on-boardthe apparatus where the resistor is located still exists.

BRIEF SUMMARY OF THE INVENTION

[0012] The embodiments of the invention are directed to a structure fora semiconductor resistive element and the respective manufacturingprocess.

[0013] In accordance with one embodiment, resistive structures capable,for example, of detecting the voltage present on an electrode (collectoror drain) of the power component in monolith integrated semiconductordevices are provided.

[0014] The embodiments of the invention improve the previously knownsolutions in terms of electrical performance and manufacturing process.For this purpose, according to the currently preferred embodiment of theinvention, a second epitaxial layer is grown on a first epitaxial layerand then a layer with a higher doping concentration than the secondepitaxial layer, positioned over a buried region, is obtained byphotolithography, ion implantation and diffusion. The buried region isof opposite conductivity type to the first epitaxial layer to define aresistive element. Ideally, the buried region includes subregions thatare connected in marginal continuity relationship.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

[0015] The invention will now be described, by way of example only, withreference to the accompanying drawings, wherein:

[0016]FIGS. 1, 4 and 7 are three schematic plan views of respectiveembodiments of the structure according to the invention, FIGS. 2, 5 and8 are essentially cross-sectional views, according to line II-II in FIG.1, line V-V in FIG. 4 and line VII-VII in FIG. 7, respectively,

[0017]FIGS. 3, 6 and 9 are additional cross-sectional views, accordingto line III-III in FIG. 1, line VI-VI in FIG. 4 and line IX-IX in FIG.7, respectively, and

[0018]FIGS. 10, 11 and 12 are three current/voltage diagrams forexemplifying various behaviors of a resistive element structureaccording to the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0019] In the accompanying Figures, numeral 1 generally refers to asemiconductor substrate (e.g., silicon) presenting a high dopingconcentration of the n type.

[0020] On this semiconductor substrate 1, an epitaxial layer 2 is grownof a homologous type (i.e., also with conductivity of the n type) with aconcentration and thickness defined (in a manner known per se) accordingto the voltage class in which the structure made according to theinvention is intended to operate.

[0021] A region, generally indicated with numeral 3, of the p type,where p type is a second type of conductivity opposite to the first typeof conductivity which is of the type n in the embodiment illustratedherein, is made by ion implantation and subsequent diffusion process.

[0022] The region 3 is intended to form the body of the resistiveelement or resistor and, in other regions of the chip, the buried baseof a high voltage BJT transistor as well as the buried insulatingregion.

[0023] The specific implementation methods of the region 3 are the mainelement of distinction between the three embodiments, illustrated inFIGS. 1 to 3 (a first embodiment), FIGS. 4 to 6 (a second embodiment),and FIGS. 7 to 9 (a third embodiment), respectively.

[0024] With reference to this, it will be noted that FIGS. 1, 4 and 7refer to the conditions attained after the implantation process, whileFIGS. 2-3, 5-6 and 8-9 of the respective embodiments refer to theresults obtained after the diffusion process.

[0025] In the first embodiment shown in FIGS. 1 to 3, the region 3 isessentially made in the form of a sort of cylindrical bar with endregions rounded as a result of the diffusion process. Consequently, inthis first embodiment, region 3 is essentially uniform along its entiredevelopment in the main direction of extension.

[0026] Conversely, in the second embodiment shown in FIGS. 4 to 6, theregion 3 is made in the form of a set of subregions which, uponimplantation (see FIG. 4) have an extension equal to L2 and arereciprocally separated by a distance D2. The extension and distance areobviously always defined in the main direction of extension of theregion 3, while the concerned subregions (the same is true in generalfor the region 3 shown in FIGS. 1 to 3) present a width equal to W2 andtransversally with respect to region 3.

[0027] By effect of the subsequent diffusion treatment, said subregionsexpand assuming the appearance of spheroids reciprocally connected in amarginal continuity relationship, i.e., so that spheroids arereciprocally approximately tangent, while being actually connected,consequently reciprocally secant, along the entire development of theregion 3 in the main direction of extension.

[0028] The third embodiment shown in FIGS. 7 to 9 can be seen as a sortof combination of the two embodiments illustrated previously. In thiscase, region 3 is partially formed by a cylindrical bar with roundedends, essentially similar to the bar for the region 3 in the firstembodiment shown in FIGS. 1 to 3, but “shorter”. This shorter bar isconnected in a marginal continuity relationship with a plurality ofspheroids 3, which are essentially similar to those present in thesecond embodiment in FIGS. 4 to 6, these spheroids forming the remainingpart of the region 3.

[0029] Also in this case, the shorter bar is initially made with alength equal to L3, so to be at a distance from the other homologoussubregions, which are essentially identical to those shown in FIG. 4.The subsequent diffusion treatment also in this case provides marginalcontinuity as a result (see FIGS. 5 and 6).

[0030] Regardless of the methods adopted for making the region 3, anadditional semiconductor epitaxial layer of the n type (herein referencewill be made to silicon as a non-limiting example) is deposited on theregion 3 and the underlying substrate 2. This will confer to region 3the characteristic of a buried region.

[0031] This second epitaxial layer of the n type (i.e., the first typeof conductivity, in the example illustrated here, which is just anexample) is indicated with numeral 4 in the accompanying drawings.

[0032] Subsequently, a layer n, indicated with numeral 5, is created byphotolithography, ion implantation and diffusion on the new surface thuscreating a second region. This layer has a higher doping concentrationwith respect to the epitaxial layer 4.

[0033] Specifically, the layer 5, the second region, is positioned overthe buried region 3.

[0034] Low resistivity regions of the p type, indicated with numeral 6and intended to form a low resistivity deep contact of the resistorcomprised of the region 3 and, in other regions of the chip, the deepbase contact of the high voltage BJT, so to complete the insulatingregion in the control area, are then formed again by photolithography,ion implantation and diffusion.

[0035] At this point, the manufacturing process continues and thestructure is completed with the required layers (e.g., with aninsulating layer of silicon dioxide, indicated with numeral 7). Finallythe electrical contacts 8 and the associated electrodes are created byphotolithography and deposition.

[0036] Those skilled in the art will appreciate the fact that themanufacturing process just described involves carrying out operationsand treatment phases which are per se individually well-known in the artand consequently do not require a detail description in herein.

[0037] By adopting the described structure, a resistive element can beproduced which demonstrates different behaviors according to the voltageapplied across its terminals (practically according to the voltageapplied between the electrodes 8 shown in FIGS. 3, 6 and 9).

[0038] Particularly, by forming the region 3 with a substantiallyuniform development in its main direction of extension (as shown in FIG.1 and 3) and suitable length, a resistor can be produced having acharacteristic which is substantially linear over the entire substratevoltage range, i.e., a resistive element whose characteristic is of thetype shown in the diagram in FIG. 10.

[0039] Conversely, by forming the region 3 according to the embodimentillustrated in FIGS. 4 to 6, i.e., in the form of subregions which areoriginally separate after implantation and then marginally joined aftersubsequent diffusion, the resistive element presents a characteristicthat is comparable to that of a jfet, i.e., a characteristic of the typeshown in the diagram of FIG. 11.

[0040] In this case, the behavior of the structure is regulated by thewidth W2 in addition to the length L2 of the single implanted subregionsand by the distance D2 at which they are implanted.

[0041] An embodiment of the type illustrated in FIGS. 7 to 9 can be usedto make a resistive element presenting a characteristic which is to acertain extent intermediate between that shown in FIG. 10 and that shownin FIG. 11, i.e., a characteristic of the type shown in FIG. 12.

[0042] Specifically, when an embodiment of the type shown in FIGS. 7 to9 is adopted, the resistance value of the linear section of theelectrical characteristics (see the characteristic part essentiallycomprised between the abscissa values equal to 50V and 150V in thediagram in FIG. 12) can be determined by operating on the value of thelength L3.

[0043] A behavior of the type shown in FIGS. 11 and 12, namely, forms alinear voltage/current characteristic (constant resistance) for acertain initial range of voltage values, and a subsequent markedincrease of the resistance value determined by the substantialstabilization, according to a typically asymptotic trend, of theintensity of the current through the resistive element for voltagevalues exceeding said initial field. Also, the behavior can beadvantageously exploited in the context of techniques for controllingthe step response in high voltage devices, such as electronic ignitionsystems.

[0044] This all according to the methods better described in aco-pending U.S. Patent Application, entitled System and Process forControlling the Step Response of Electronic Components, filedconcurrently herewith in the name of the Applicant, and which isincorporated in its entirety herein by reference.

[0045] In any case, the non-limiting embodiments described in theinstant application can be used to make a resistive element which is notaffected by surface MOS parasite effects, thanks to the layer noverlying the body of the resistor which prevents the formation ofsurface conductive channels due to charge possibly contained in thesilicon oxide.

[0046] The structure according to the invention can be integrated in anintegrated power device (e.g., of the PIC or VIPower type) since all thelayers used to make the component are already present in the processsequence.

[0047] Furthermore, the structure according to the invention presents asurface area which is considerably reduced when compared with prior artresistors, since it is possible to obtain high resistance values,particularly by using an embodiment which provides a performancecomparable to that of a jfet.

[0048] Naturally, numerous changes can be implemented to theconstruction and embodiments of the invention herein envisaged, withoutdeparting from the scope of the invention. This particularly but notexclusively refers to the possibility of using different semiconductormaterials, e.g., SiC, for making the various layers/regions of thestructure according to this invention, and making the layers/regionsdescribed above with types of conductivity (p or n) which are oppositewith respect to those described: e.g., layers 1, 2, 4 and 5 of the ptype and the regions 3 and 6 of the n type. In this sense, theexpressions “first type of conductivity” and “second type ofconductivity” can refer both to conductivity of the n type and toconductivity of the p type, notwithstanding the opposite character ofthe first type and of the second type of conductivity.

[0049] From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims and the equivalents thereof.

1. A structure for a semiconductor resistive element, comprising: afirst layer with a first type of conductivity; a region with a secondtype of conductivity arranged on said first layer, said region definingthe resistive element proper; a second layer with said first type ofconductivity grown on said first layer to make said region a buriedregion; and an additional layer of said first type of conductivity andhaving a higher concentration with respect to said second layer, saidadditional layer positioned above said buried region.
 2. The structureof claim 1, comprising a substrate of said first conductivity with ahigh doping concentration on the side of said first layer opposite tosaid buried region.
 3. The structure of claim 1 wherein said buriedregion presents a main direction of extension and, at least in part, adevelopment which is substantially uniform in said main direction ofextension.
 4. The structure of claim 3 wherein said buried regionpresents a development that is substantially uniform throughout itsextension in said main direction.
 5. The structure of claim 1 whereinsaid buried region comprises, at least in part, subregions that arereciprocally connected in a marginal continuity relationship.
 6. Thestructure of claim 5 wherein said subregions present an approximatelyspheroidal conformation.
 7. The structure of claim 5 wherein said buriedregion integrally consists of said subregions reciprocally connected ina marginal continuity relationship.
 8. The structure of claim 3 whereinsaid buried region presents, in part, a development that issubstantially uniform in said main direction of extension and, in theremaining part, is formed by subregions that are reciprocally connectedin a marginal continuity relationship.
 9. The structure of claim 1,comprising at least one additional region with said second conductivityand with low resistivity forming a contact to said buried region. 10.The structure of claim 1 wherein said first and said second type ofconductivity are of the n type or the p type, respectively.
 11. Aprocess for making a structure for a semiconductor resistive element,comprising the steps of: forming a first layer with a first type ofconductivity; forming on said first layer a region with a second type ofconductivity defining the resistive element proper; providing on saidfirst layer a second layer with said first type of conductivity so tomake said region a buried region; and forming an additional layer withsaid first type of conductivity with a higher concentration with respectto said second layer, said additional layer being positioned above saidburied region.
 12. The process of claim 11, comprising the step offorming a substrate of said first conductivity with a high dopingconcentration on the side of said first layer opposite to said buriedregion.
 13. The process of claim 1 1, comprising the step of formingsaid buried region by bestowing on it a main direction of extension and,at least in part, a development that is substantially uniform in saidmain direction of extension.
 14. The process of claim 13, comprising thestep of forming said buried region with a development which issubstantially uniform throughout its extension in said main direction.15. The process of claim 11, comprising the step of forming said buriedregion, at least in part, with subregions that are reciprocallyconnected in a marginal continuity relationship.
 16. The process ofclaim 15, comprising the step of forming said subregions with anapproximately spheroidal conformation.
 17. The process of claim 15,comprising the step of forming said buried region integrally in the formof said subregions reciprocally connected in a marginal continuityrelationship.
 18. The process of claim 13, comprising the step offorming said buried region, in part, with a development that issubstantially uniform in said main direction of extension and, in aremaining part, is formed by subregions that are reciprocally connectedin a marginal continuity relationship.
 19. The process of claim 15,comprising the step of forming said subregions as separate subregions byimplantation, obtaining said marginal continuity relationship bysubsequent diffusion.
 20. The process of claim 11, comprising the stepof making by epitaxial growth at least one layer out of: said firstlayer; and said second layer.
 21. The process of claim 11, comprisingthe step of making said additional layer by photolithography, ionimplantation and diffusion.
 22. The process of claim 11, comprising thestep of forming at least one additional region with said second type ofconductivity and low resistivity to form a contact with said buriedregion.
 23. The process of claim 22 wherein said at least one additionalregion is formed by photolithography, ion implantation, and diffusion.24. A semiconductor resistive structure comprising: a semiconductorsubstrate of a first type of conductivity having a first dopingconcentration; a first layer of a first type of conductivity having asecond doping concentration deposited on the semiconductor substrate; afirst region of a second type of conductivity located in a first area ofthe first layer to form a resistive structure of a cross-section and alength having a resistive behavior; a second layer of a first type ofconductivity having a third doping concentration deposited on the firstlayer; a second region of a first type of conductivity having a fourthdoping concentration located in a second area of the second layerwherein the second area is located above the first area; first andsecond deep contacts of a second type of conductivity coupled to thefirst region; and first and second electrical contacts coupled to thefirst and second deep contacts, respectively.
 25. The semiconductorresistive structure of claim 24 wherein the fourth doping concentrationof the second region is greater than the third doping concentration ofthe second layer.
 26. The semiconductor resistive structure of claim 24wherein the cross-section of the first region is substantially uniformfor the length of the first region.
 27. The semiconductor resistivestructure of claim 24 wherein the cross-section of the first region issubstantially uniform for a first portion of the length of the firstregion and periodic for a second portion of the length of the firstregion.
 28. The semiconductor resistive structure of claim 24 whereinthe cross-section of the first region is periodic for the length of thefirst region.
 29. The semiconductor resistive structure of claim 24wherein the resistive behavior is a constant function of a first rangeof voltage and current.
 30. The semiconductor resistive structure ofclaim 24 wherein the resistive behavior is a linear function of a secondrange of voltage and current.